1)A Drain Current Extraction Technique using Source Parasitic Resistance and Inductance in SiC Power MOSFETs,IEEE Transactions on Power Electronics: DOI 10.1109/TPEL.2023.3345315;
2)A Design Method of Partially Interleaved Winding Structure with Low Leakage Inductance for Planar Transformer Application,IEEE Transactions on Power Electronics,10.1109/TPEL.2023.3242109
3)A Self-Adaptive Measurement System for IGBT Collector Current using Package Parasitics, IEEE Transactions on Industrial Electronics, DOI 10.1109/TIE.2020.3001853